1. Field of the Invention
The invention relates to a memory row decoder and more particularly to a memory row decoder with reduced gate induced drain leakage (GIDL) current.
2. Description of the Related Art
Gate induced drain leakage (GIDL), with regards to off-state current, constitutes a serious constraint in scaled down CMOS device. GIDL is induced by strong electric field between the gate and drain, and increases exponentially due to reduced gate oxide thickness. Since increased integration of semiconductor devices requires thinner gate oxide layer between a substrate and gate, GIDL is an issue when MOS transistors are scaled towards the deep sub-micrometer regime.
FIG. 1 is an exemplary diagram showing source-to-drain current ISD as a function of source-to-gate voltage VSG for a PMOS transistor, to illustrate GIDL effect. As shown, when source-to-gate voltage VSG for the PMOS transistor falls below threshold voltage Vt, only sub-threshold current flows in the source-to-drain path. This current decreases with VSG down to −VA. The value of −VA may range from −1V to −3V, dependent on fabrication technology and process. However, if the source-to-gate voltage VSG is more negative than −VA, a leakage current (GIDL) occurs and increases significantly with decreased VSG. It is noted the drawing and discussion here are for a PMOS transistor, and can be analogized to NMOS by replacing the source-to-drain current ISD with drain-to-source current IDS and source-to-gate voltage VSG with gate-to-source voltage VGS.
FIG. 2 is a schematic diagram of a conventional memory row decoder 200, to which one of word lines of a memory can be coupled and enabled selectively. As shown, the memory row decoder driver 200 includes an enhancement PMOS transistor, mep1, having its source-to-drain path coupled between a signal terminal 21 and an output terminal 23 to which is coupled the associated word line WL of the memory row decoder 200. The substrate 22 of mep1 is coupled to a terminal 24 to which is applied a fixed potential VPP. The source-to-drain paths of enhancement NMOS transistors men1 and men2 are coupled in parallel between the output terminal 23 and a terminal 25 to which is applied another fixed potential VNN relatively negative to VPP. The substrates 26 and 27 of transistors men1 and men2 are also returned to VNN. A first partially decoded signal, bMWL, is applied to the gates of transistors mep1 and men1 and a second partially decoded signal, WLDV, is applied to the signal terminal 21. A reset signal WLRST (typically the inverse of WLDV) is applied to the gate of men2 to enable the word line WL to be selectively clamped to VNN for certain input signal conditions.
The circuit of FIG. 2 is used to activate a selected word line. When the first partially decoded signal bMWL is low and the second partially decoded signal WLDV is high (and the reset signal WLRST is low), a high potential (e.g., VPP) is applied to the word line, activating it and enabling the memory cell transistors with gates coupled to the word line. The memory row decoder 200 is accordingly deemed to operate in a “selected” mode. When the first partially decoded signal bMWL is high and the second partially decoded signal WLDV is a low (and WLRST is high), a low potential (e.g., VNN) is applied to the word line WL and the memory row decoder 200 is deemed to operate at an “unselected” mode since the memory cell transistors with gates coupled to the word line are turned off. Thus, the memory row decoder 200 may be used to apply either an activation voltage (e.g., VPP) to the word line WL or a deactivation voltage (e.g., VNN) to the word line WL.
As shown, when the memory row decoder 200 is in an unselected mode, the source-to-gate voltage of the enhancement PMOS transistor mep1 is (VNN-VPP). In memory design, the level of VNN is chosen relatively negative to the bulk voltage of other transistors outside the memory for the purpose of minimizing the off-state sub-threshold current of the transistors in the memory. However, this makes (VNN-VPP) more negative and results in increased off-state sub-threshold current due to GIDL effect and accordingly more power consumption.
It is thus important to provide a memory row decoder with reduced GIDL current to reduce power consumption.